Search This Blog

Tuesday 23 April 2019

Computer Science Links To Study For GATE, NET, SET and Assistant professor, degree college lecturers etc..

computer organization
https://www.youtube.com/watch?v=B6rqMbArcew&list=PLV8vIYTIdSnar4uzz-4TIlgyFJ2m18NE3

https://www.youtube.com/channel/UCJihyK0A38SZ6SdJirEdIOw/playlists

https://www.youtube.com/watch?v=VZqSCFt6OsM&list=PLr3OnN7Kdzeh0xHH_OaEzzk21vn6LIrw1
fuzzy logic:
https://www.youtube.com/watch?v=0kgEjAAjxM8&list=PLd-w81Yu7F04xO9vXaSp4mdlBGXoJtkFz
https://www.youtube.com/watch?v=sukorfvuWYw

computer networks
https://www.youtube.com/watch?v=4D55Cmj2t-A&list=PLxCzCOWd7aiGFBD2-2joCpWOLUrDLvVV_
https://www.youtube.com/watch?v=XsISArkVCHI&list=PLS8ACsmFCpmSal81E89wePaEnyCFPS3mp

Compiler design
https://www.youtube.com/watch?v=otsHS_CkQ2c&list=PLd-w81Yu7F051eey94_J94kODhu8tgmCp&index=2

https://www.youtube.com/watch?v=3hPilFvVVLk&list=PLV8vIYTIdSnbbJyE9osMAUQOX3mvXKlOc

https://www.youtube.com/playlist?list=PLayxKQoyjT3-dtfq724IRZjYtH9_EoVOx
1. Page table, TLB is stored in MMU(memory management unit)
2. Little endian --lower byte in lower address
3. interface is a processing unit and contains buffer
4. physical memory is always divided into frames
cache is divided into blocks
virtual memory is divided into pages
page and frame size should be same
5. cache is made up of static RAM (Flip Flops and transistors),
RAM is made up of    DRAM (capacitors and transistors)
looping variable can be kept in cache.
6.  instruction fetch is divided into instruction decode, operand fetch
in instruction fetch cycle --
address of next instruction is stored in PC. PC is only connected to internal bus.
so the contents of PC are transferred to MAR( MAR is connected to internal and external bus) and PC is incremented
the address in MAR is fetched in main memory and data at that address is stored in MDR.
data in MDR is decoded and transferred to IR

7. the instruction to which you will go after jump instruction is called branch target
I1 is stored in 1000 address and I2 stored in 1001 and so on
when I1 is executing PC will contain 1001
if I1 is JMP 3(PC) then PC will contain 1001+3 = 1004 so after I1 and I4 instruction at 1004 will be executed.
8. flag register in 8085 or 8086 is 8 bit register ===sign flag (set when result is -ve), zero flag,parity flag, carry flag, overflow flag (if carry in and carry out is different)
9. CALL will push the value of PC onto stack (ex: PC will store the address of next instruction in main() after the function call)
RET will pop the value of PC in subroutine call
10. the assembler stores the names of identifiers and their values in symbol table.
11. Bus configuration techniques 
Inorder for CPU to communicate to MM or I/O using common system bus is
we can use seperate control signals (MRD, IORD, MWR,IOWR) =called I/O mapped devices so CPU sends control signal on control lines and address on address line requiring less address lines than memory mapped I/O
or
we can use different address for memory and I/O = called Memory mapped I/O
CPU can maintain separate bus for MM and for I/O == called isolated I/O

12. Different ways to access I/O devices:
1. Program controlled I/O: here the CPU continuously checks the status flag of I/O interface (POLLING). Once the status flag becomes zero then the input is available. VERY SLOW AND WASTE
2. Interrupt Driven I/O : CPU has INTR and INTA part of control lines to receive and acknowledge interrupt signals. once status flag becomes zero, I/O interface interrupts CPU after every 4bytes.
For example: if data has to be transferred from Hard disk to main memory. Hard disk will send 4 bytes of data to I/O interface. Then I/O interface interrupts the CPU as the data to be transferred is available in I/O interface.CPU will initiate transfer of data from I/O interface to MM. this repeats for every 4 bytes

Using Daisy chaining using single interrupt line CPU can service n different I/O devices.
3. Direct Memory Access: FASTER.
DMA is a device conntected to DMA controller/interface that transfer data a block of memory mostly 512 bytes transfer from hard disk to main memory
For example: if data has to be transferred from Hard disk to main memory.CPU will tell DMA that u need to transfer 1 KB of data from HDD to main memory initially. After transferring 1KB DMA interrupts CPU

DMA controller/interface has address register, counter register and buffer register. CPU will put the address of HDD (starting address of data to be transferred) in address register. and number of bytes to be transferred in count register

Using system call or software interrupt we can change the CPU from user mode to kernel mode

how the processor ignore other interrupts when processor is servicing an interrupt
Turn off  the interrupt request line if the interrupt is maskable(RST 5.5,6.5,7.5 in 8085)
disable the devices from sending interrupts
by using edge triggered request lines


Posted by at
Labels: , , , , , , , , ,

No comments:

Post a Comment

Subscribe to: Post Comments (Atom)